Career Summary

I’m a C++ developer with keen interest towards working with different CPU architectures and the associated ecosystems. My current and past varied experiences have enabled me learn about the various facets of the semiconductor industry.

My specialities range from experience in

  • Custom processor (fast models) development
  • SoC functional modelling of sub-systems, peripherals
  • Architectural exploration of cache systems, imaging sub-systems, bus protocols
  • Contributor to the Accellera-CCI (IEEE) Working Group
  • Developing CXX tools targeting Instruction Stream Generators (ISGs) for chip verification activities
  • Protocol modelling using Synthesizable subset of SystemC (knowhow on Forte’s Cynthesizer tooling)
  • Modelling using SystemC-AMS

Before to joining semiconductor industry, I’ve worked for the defence and commercial robotics industry where-in my primary works were related to Embedded and Control Systems, Robotics & AI.

I’ve also participated in various forums - ISCUG, DVCON, NASCUG and presented my works over there. I’ve prepared information on tools required for the Press Releases.

During my free time, I explore various technologies and upcoming trends. Am an active blogger and more about my works, contributions, learnings, interests, one may find it here - https://vsphaneendrapaluri.github.io/ (you are reading this!)

Domains Interests

  • Virtual Prototying & Co-Simulations
  • CPU Architectures
  • Robotics, AI

Professional Experience

  • Infineon Technologies (July, 2016 - Present)
    • Designation: Senior Staff Engineer
    • Locations: Bengaluru (IND)
  • Test & Verification Solutions (September, 2014 - March, 2016)
    • Designation: Senior Engineer
    • Locations: Bengaluru (IND), Boras (SWE), San Jose (USA)
  • CircuitSutra Technologies (March, 2011 - September, 2014)
    • Designation: Member of Technical Staff
    • Locations: Bengaluru (IND)
  • HiTech Robotic Systems (July, 2019 - March, 2011)
    • Designation: Research Developer
    • Locations: Bengaluru (IND)

Conference Participations

  • Event : DVCON India, 2014
    Tutorial: SystemC-AMS based methodologies for the design and verification of heterogeneous systems
    Session : Overview of SystemC-AMS
    Link : DVCON India 2014 Conference Program

  • Event : NASCUG, 2013
    Paper : Co-Author for AXI4 Protocol Development Using HLS Tool

  • Event : ISCUG, 2012
    Tutorial: The New SystemC Standard - IEEE 1666-2011
    Session : Speaker for ‘Accellera SystemC-CCI Working Group Updates’
    Link : ISCUG 2012: Agenda

Education

Master of Technology (M.Tech)

  • University: Indian Institute of Technology Roorkee [Class 2009]
  • Department: Department of Electrical Engineering
  • Specialization: System Engineering and Operations Research
  • Dissertation Title: Closed-Loop OFDM Systems

Bachelor of Technology (B.Tech)

  • Electronics and Communications Engineering, C V R College of Engineering [Class 2007]

Contact Information